1. Field
The invention relates to thermosetting resin compositions with low coefficient of thermal expansion are provided herein.
2. Brief Description of Related Technology
Low dielectric constant (“low-k”) dielectric materials (or interlayer dielectric layers, “ILD's”) continue play an important role in the future development of advanced integrated circuit manufacturing. Low-k ILD's are used in integrated circuit manufacturing to insulate copper interconnects from their surroundings, ensuring less cross talk between interconnections. Cross talk is a common problem in integrated circuit manufacturing, as it causes malfunction in the circuit. Cross talk becomes even more pronounced as the size of the integrated circuit continues to shrink.
As the industry continues to seek advanced materials for circuit boards (moving from ceramic to composite), semiconductor chips that are inherently more fragile (due to their ever-reduced thickness) though with greater computing capability, finer pitch, increased density of solder ball placement and smaller diameter solder balls themselves, and increased reflow temperatures due to the conversion of leaded solders to lead free solders, greater stresses due to warpage and shock are observed in the semiconductor packages being designed today than ever before.
Conventional commercial underfill sealant materials, such as low coefficient of thermal expansion (“CTE”), high modulus, epoxy-based underfill sealant materials appear to be incapable of providing the necessary protection against package stresses to prevent damage to the fragile low-k ILD's. The low-k ILD's, being fragile in nature, are generally weaker and more brittle than conventional ILD materials, such as silicon oxides, silicon nitrides, fluorinated silicon glass, and the like, and as a result lead to fracture and cracks during thermal excursions due to induced stresses.
In addition, liquid compression molding materials could benefit from a similar set of physical properties. For instance, in fan-out wafer level packaging applications in the semiconductor packaging industry, protective materials are coated on a metal carrier on which is disposed one or more diced silicon dies picked and then placed thereon. The gaps and edges around the silicon dies are filled with the protective material to form a molded wafer.
Conventional materials used to form the molded wafer have either not possessed the desired physical properties to offer improved resistance to wafer warpage, or have not lent themselves to application by liquid compression molding techniques.
It would be desirable therefore to provide encapsulation by liquid compression molding to silicon wafers materials suitable for application, which are thermosetting resin compositions capable of providing improved resistance to wafer warpage.
In the past, silica fillers have been used to accommodate the mismatch of CTE between semiconductor chips and circuit boards or carrier substrates. One way to reduce CTE of a silica filled thermosetting resin composition is to increase the amount of the silica used. However, increasing the silica content comes with a price; the viscosity tends to increase, oftentimes to levels rendering the composition unsuitable for some applications. Sometimes the surfaces of the silica fillers have been modified with hexamethyldisiloxane, dimethoxy silane and 3-glycidoxypropyltrimethoxy silane to name a few surface modifiers. Despite the use of these surface modifiers, the CTE of silica-filled thermosetting resin compositions have not approached a sufficiently low level to reach certain desired physical property targets.
It would be desirable therefore to provide electronic packaging materials suitable for advanced applications, such as thermosetting resin compositions useful for FC underfill sealant materials, which are compatible for use with low-k ILD's and reduce the internal package stresses that lead to ILD cracking failures. In addition, it would be desirable to provide electronic packages assembled with such thermosetting resin compositions, provide methods of manufacturing such electronic packages that provide enhanced physical properties, and provide methods of providing thermosetting resin compositions having a physical property profile in terms of reduced modulus and CTE that make such compositions particularly attractive to high stress FC underfill sealant applications in semiconductor packaging.